[coreboot-gerrit] Change in coreboot[master]: md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M
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md/cedarisland_crb: exclude the consequences of reconfig GPIO by FSP-M

As with the FSP-M for Intel Skylake-SP [1], we should be sure that
after romstage the pads will be configured according to the config
from gpio.h only. This patch sets the GPIO configuration from gpio.h
using the soc/intel/common/gpio.c driver again in ramstage.

[1]

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40735/1

diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
new file mode 100644
index 0000000..f4c716e
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* configure Lewisburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}