2 Feb
2021
2 Feb
'21
10:05 p.m.
Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 )
Change subject: soc/amd/cezanne: populate some FSP-M UPDs ......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/romstage.c:
https://review.coreboot.org/c/coreboot/+/50239/comment/2bf27d15_50938c28 PS2, Line 19: 1
no. in the mmio case the spacing between the registers might be either 1 or 4 bytes. […]
Cezanne doesn't support a stride of 1 though. So I don't think we should be passing in an unsupported value.
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Gerrit-Project: coreboot
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