Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38715 )
Change subject: mb/google/volteer: use new tigerlake memory config ......................................................................
mb/google/volteer: use new tigerlake memory config
Some of the common memory code that was being performed in mainboard has moved into the soc to reduce redundant code. This change adapts volteer to use tigerlake's new common code.
Define GPIO_MEM_CH_SEL to use for determining if all of memory is populated or only half.
- if value read from GPIO_MEM_CH_SEL is 1, only half of DRAM is populated
- if value read is 0, or GPIO_MEM_CH_SEL is not defined, all of DRAM is populated
BUG=b:145642089, b:145238504, b:145564831 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel, "cat /proc/meminfo" and verify it reports "MemTotal: 8038196 kB".
Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- A src/mainboard/google/volteer/romstage.c A src/mainboard/google/volteer/variants/baseboard/memory.c 2 files changed, 114 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38715/1
diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c new file mode 100644 index 0000000..ded300c --- /dev/null +++ b/src/mainboard/google/volteer/romstage.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/meminit_tgl.h> +#include <soc/romstage.h> +#include <string.h> +#include <variant/gpio.h> + +#include <fsp/soc_binding.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct mb_lpddr4x_cfg board_cfg; + bool half_populated = false; + + memset(&board_cfg, 0, sizeof(board_cfg)); + variant_memory_params(&board_cfg); + + /* + * If GPIO_MEM_CH_SEL is defined, check it to see if we are only + * populating half of the memory slots. + * + * The gpio will read as 1 if half populating DRAM, and will read as + * 0 if using all available memory slots. + */ +#ifdef GPIO_MEM_CH_SEL + half_populated = gpio_get(GPIO_MEM_CH_SEL); +#endif + board_cfg.half_populated = half_populated; + board_cfg.spd.read_type = READ_SPD_CBFS; + board_cfg.spd.spd_spec.spd_index = variant_memory_sku(); + + meminit_lpddr4x(mem_cfg, &board_cfg); +} diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c new file mode 100644 index 0000000..6379c54 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +/* DQ byte map */ +static const struct mb_lpddr4x_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 2, 3, 4, 5, 6, 7, /* Byte 0 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ + { 7, 2, 6, 3, 5, 1, 4, 0, /* Byte 2 */ + 10, 8, 9, 11, 15, 12, 14, 13 }, /* Byte 3 */ + { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 4 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 5 */ + { 7, 0, 1, 6, 5, 4, 2, 3, /* Byte 6 */ + 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ + { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 0 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ + { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ + 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ + { 3, 2, 1, 0, 7, 4, 5, 6, /* Byte 4 */ + 15, 14, 13, 12, 8, 9, 10, 11 }, /* Byte 5 */ + { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ + 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .ect = 0, /* Disable Early Command Training */ + + .half_populated = 0, /* Use all of memory */ +}; + +void variant_memory_params(struct mb_lpddr4x_cfg *bcfg) +{ + memcpy(bcfg->dq_map, baseboard_memcfg.dq_map, + sizeof(baseboard_memcfg.dq_map)); + + memcpy(bcfg->dqs_map, baseboard_memcfg.dqs_map, + sizeof(baseboard_memcfg.dqs_map)); + + bcfg->ect = baseboard_memcfg.ect; + bcfg->half_populated = baseboard_memcfg.half_populated; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +}