Felix Held has uploaded this change for review. ( https://review.coreboot.org/27674
Change subject: andybridge/raminit_common: use MCHBAR32 macro consistently ......................................................................
andybridge/raminit_common: use MCHBAR32 macro consistently
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 542 insertions(+), 662 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27674/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 44f7f6d..2a5f09c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -72,10 +72,10 @@
static void toggle_io_reset(void) { /* toggle IO reset bit */ - u32 r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); + u32 r32 = MCHBAR32(0x5030); + MCHBAR32(0x5030) = r32 | 0x20; udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); + MCHBAR32(0x5030) = r32 & ~0x20; udelay(1); }
@@ -623,7 +623,7 @@ static void wait_428c(int channel) { while (1) { - if (read32(DEFAULT_MCHBAR + 0x428c + (channel << 10)) & 0x50) + if (MCHBAR32(0x428c + (channel << 10)) & 0x50) return; } } @@ -641,15 +641,14 @@ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2;
/* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01;
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4210 + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001); + MCHBAR32(0x4284 + 0x400 * channel) = 0x400001; wait_428c(channel); }
@@ -736,27 +735,26 @@ }
/* DRAM command MRS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | (reg << 20) | val | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f000; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | (reg << 20) | val | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command MRS */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | (reg << 20) | val | 0x60000); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4234 + 0x400 * channel) = 0x41001; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | (reg << 20) | val | 0x60000; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command MRS */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | (reg << 20) | val | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001); + MCHBAR32(0x4228 + 0x400 * channel) = 0x0f000; + MCHBAR32(0x4238 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | (reg << 20) | val | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 0x80001; }
static u32 make_mr0(ramctr_timing * ctrl, u8 rank) @@ -789,8 +787,7 @@
static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) { - write_mrreg(ctrl, channel, rank, 0, - make_mr0(ctrl, rank)); + write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); }
static u32 encode_odt(u32 odt) @@ -880,19 +877,19 @@ }
/* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4e20, 0x7); - write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001); - write32(DEFAULT_MCHBAR + 0x4e00, 0x60002); - write32(DEFAULT_MCHBAR + 0x4e10, 0); + MCHBAR32(0x4e20) = 0x7; + MCHBAR32(0x4e30) = 0xf1001; + MCHBAR32(0x4e00) = 0x60002; + MCHBAR32(0x4e10) = 0;
/* DRAM command ZQCL */ - write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003); - write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001); - write32(DEFAULT_MCHBAR + 0x4e04, 0x60400); - write32(DEFAULT_MCHBAR + 0x4e14, 0x288); + MCHBAR32(0x4e24) = 0x1f003; + MCHBAR32(0x4e34) = 0x1901001; + MCHBAR32(0x4e04) = 0x60400; + MCHBAR32(0x4e14) = 0x288;
/* execute command queue on all channels ? */ - write32(DEFAULT_MCHBAR + 0x4e84, 0x40004); + MCHBAR32(0x4e84) = 0x40004;
// Drain FOR_ALL_CHANNELS { @@ -917,12 +914,12 @@ wait_428c(channel);
/* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4284 + 0x400 * channel) = 0x1;
// Drain wait_428c(channel); @@ -967,8 +964,7 @@ case 3: slot320c[slot] = (ctrl->timings[channel][2 * slot].val_320c + - ctrl->timings[channel][2 * slot + - 1].val_320c) / 2 + + ctrl->timings[channel][2 * slot + 1].val_320c) / 2 + full_shift; break; } @@ -1088,37 +1084,31 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4040c01; + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x100f | ((ctrl->CAS + 36) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
/* DRAM command MRS * write MR3 MPR disable */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
wait_428c(channel); } @@ -1127,8 +1117,7 @@ int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((read32 - (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + + return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + ((timA / 32) & 1) * 4) >> (timA % 32)) & 1); } @@ -1200,7 +1189,7 @@ if (upperA[lane] < rn.middle) upperA[lane] += 128; printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, slotrank, lane, rn.start, rn.middle, rn.end); } }
@@ -1222,8 +1211,8 @@ test_timA(ctrl, channel, slotrank); FOR_ALL_LANES { statistics[lane][timA_delta + 25] += - does_lane_work(ctrl, channel, slotrank, - lane); + does_lane_work(ctrl, channel, slotrank, + lane); } } } @@ -1371,34 +1360,32 @@ int upperA[NUM_LANES]; struct timA_minmax mnmx;
- wait_428c(channel); + wait_428c(channel);
- /* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + /* DRAM command PREA */ + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 1;
- write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001); + MCHBAR32(0x3400) = (slotrank << 2) | 0x8001;
- ctrl->timings[channel][slotrank].val_4028 = 4; - ctrl->timings[channel][slotrank].val_4024 = 55; - program_timings(ctrl, channel); + ctrl->timings[channel][slotrank].val_4028 = 4; + ctrl->timings[channel][slotrank].val_4024 = 55; + program_timings(ctrl, channel);
- discover_timA_coarse(ctrl, channel, slotrank, upperA); + discover_timA_coarse(ctrl, channel, slotrank, upperA);
- all_high = 1; - some_high = 0; - FOR_ALL_LANES { - if (ctrl->timings[channel][slotrank].lanes[lane]. - timA >= 0x40) - some_high = 1; - else - all_high = 0; - } + all_high = 1; + some_high = 0; + FOR_ALL_LANES { + if (ctrl->timings[channel][slotrank].lanes[lane].timA >= + 0x40) + some_high = 1; + else + all_high = 0; + }
if (all_high) { ctrl->timings[channel][slotrank].val_4028--; @@ -1446,11 +1433,11 @@
printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, - ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, + lane, + ctrl->timings[channel][slotrank].lanes[lane].timA);
- write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0;
toggle_io_reset(); } @@ -1459,8 +1446,7 @@ program_timings(ctrl, channel); } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel - + 4 * lane, 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -1470,82 +1456,75 @@ int lane;
FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane, 0); - read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane); + volatile u32 tmp; + MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; + tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); }
wait_428c(channel);
/* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 4 | (ctrl->tRCD << 16)); + | 4 | (ctrl->tRCD << 16);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | (6 << 16)); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
/* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 8); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; + MCHBAR32(0x4234 + 0x400 * channel) = 0x8041001; + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 8; + MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0;
/* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4238 + 0x400 * channel) = 0x80411f4; + MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
/* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 8); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; + MCHBAR32(0x423c + 0x400 * channel) = + 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8; + MCHBAR32(0x421c + 0x400 * channel) = 0x3e0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
wait_428c(channel);
/* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240;
/* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4234 + 0x400 * channel) = (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) - | 8 | (ctrl->CAS << 16)); + | 8 | (ctrl->CAS << 16);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244); + MCHBAR32(0x4214 + 0x400 * channel) = 0x244;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x40011f4 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x40011f4 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
/* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0x240; + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); }
@@ -1558,13 +1537,11 @@ wait_428c(channel);
/* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(0x4284 + 0x400 * channel) = 1;
for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. @@ -1575,8 +1552,7 @@
FOR_ALL_LANES { statistics[lane][timC] = - read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + - 0x400 * channel); + MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); } } FOR_ALL_LANES { @@ -1589,7 +1565,7 @@ return MAKE_ERR; } printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1654,43 +1630,37 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
/* DRAM command MRS * write MR3 MPR disable */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
wait_428c(channel); } @@ -1710,45 +1680,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
/* DRAM command MRS * write MR3 MPR disable */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16);
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } } @@ -1762,22 +1726,20 @@
wait_428c(channel); /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - 8 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f207; + MCHBAR32(0x4230 + 0x400 * channel) = + 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); + MCHBAR32(0x4200 + 0x400 * channel) = 8 | (slotrank << 24); + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4000c01 | ((ctrl->CAS + 38) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 4); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f107; + MCHBAR32(0x4234 + 0x400 * channel) = + 0x4000c01 | ((ctrl->CAS + 38) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001); + MCHBAR32(0x400 * channel + 0x4284) = 0x40001; wait_428c(channel);
/* disable DQs on this slotrank */ @@ -1791,7 +1753,7 @@ int statistics[NUM_LANES][128]; int lane;
- write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2)); + MCHBAR32(0x3400) = 0x108052 | (slotrank << 2);
for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1803,8 +1765,7 @@
FOR_ALL_LANES { statistics[lane][timB] = - !((read32 - (DEFAULT_MCHBAR + lane_registers[lane] + + !((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); } @@ -1861,87 +1822,76 @@ static void adjust_high_timB(ramctr_timing * ctrl) { int channel, slotrank, lane, old; - write32(DEFAULT_MCHBAR + 0x3400, 0x200); + MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 1); + MCHBAR32(0x4288 + (channel << 10)) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001); + MCHBAR32(x4288 + 0x400 * channel) = 0x10001;
wait_428c(channel);
/* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRCD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0x8); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; + MCHBAR32(0x4234 + 0x400 * channel) = 0x8040c01; + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x8; + MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0;
/* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4238 + 0x400 * channel) = 0x8041003; + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4218 + 0x400 * channel) = 0x3e2;
/* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x8); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; + MCHBAR32(0x423c + 0x400 * channel) = + 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8; + MCHBAR32(0x421c + 0x400 * channel) = 0x3e0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
wait_428c(channel);
/* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | ((ctrl->tRP) << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | ((ctrl->tRP) << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240;
/* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0xc01 | ((ctrl->tRCD) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4234 + 0x400 * channel) = + 0xc01 | ((ctrl->tRCD) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x4000c01 | - ((ctrl->tRP + + MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; + MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + - ctrl->timings[channel][slotrank].val_4028) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60008); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + ctrl->timings[channel][slotrank].val_4028) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001); + MCHBAR32(0x4284 + 0x400 * channel) = 0x80001; wait_428c(channel); FOR_ALL_LANES { - u64 res = - read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 4); - res |= - ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 8)) << 32; + u64 res = MCHBAR32(lane_registers[lane] + + 0x100 * channel + 4); + res |= ((u64) MCHBAR32(lane_registers[lane] + + 0x100 * channel + 8)) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; @@ -1953,7 +1903,7 @@ timB); } } - write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0; }
static void write_op(ramctr_timing * ctrl, int channel) @@ -1966,15 +1916,14 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
/* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); }
@@ -1994,21 +1943,20 @@ { int channel, slotrank, lane; int err; + volatile u32 tmp;
FOR_ALL_POPULATED_CHANNELS - write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4008 + - 0x400 * channel) | 0x8000000); + MCHBAR32(0x4008 + 0x400 * channel) = + MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000;
FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel) | 0x200000); + MCHBAR32(0x4020 + 0x400 * channel) = + MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; }
/* refresh disable */ - write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); + MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8; FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2017,11 +1965,11 @@ * disable all DQ outputs * only NOP is allowed in this mode */ FOR_ALL_CHANNELS - FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 0x1080); + FOR_ALL_POPULATED_RANKS + write_mrreg(ctrl, channel, slotrank, 1, + make_mr1(ctrl, slotrank, channel) | 0x1080);
- write32(DEFAULT_MCHBAR + 0x3400, 0x108052); + MCHBAR32(0x3400) = 0x108052;
toggle_io_reset();
@@ -2035,30 +1983,29 @@ /* disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, - slotrank, 1, make_mr1(ctrl, slotrank, channel)); + slotrank, 1, make_mr1(ctrl, slotrank, channel));
- write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0;
FOR_ALL_POPULATED_CHANNELS wait_428c(channel);
/* refresh enable */ - write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8); + MCHBAR32(0x5030) = MCHBAR32(0x5030) | 8;
FOR_ALL_POPULATED_CHANNELS { - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel)); - read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel); + MCHBAR32(0x4020 + 0x400 * channel) = + ~0x00200000 & MCHBAR32(0x4020 + 0x400 * channel); + tmp = MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel);
/* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; + MCHBAR32(0x4200 + 0x400 * channel) = 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); }
@@ -2069,14 +2016,13 @@ printram("CPF\n");
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; }
FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; }
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2095,9 +2041,8 @@ program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2117,53 +2062,48 @@ } program_timings(ctrl, channel); FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0); + MCHBAR32(4 * lane + 0x4f40) = 0; }
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = 0x1f;
wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) - | 8 | (ctrl->tRCD << 16)); + | 8 | (ctrl->tRCD << 16);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | ctr | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | ctr | 0x60000;
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + MCHBAR32(0x4210 + 0x400 * channel) = 0x244; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4234 + 0x400 * channel) = + 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4244 + 0x400 * channel) = 0x389abcd; + MCHBAR32(0x4214 + 0x400 * channel) = 0x20e42;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x4001020 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x4001020 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; + MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42;
/* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = 0xf1001; + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0x240;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); FOR_ALL_LANES { - u32 r32 = - read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + - 0x400 * channel); + u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel);
if (r32 == 0) lanes_ok |= 1 << lane; @@ -2221,23 +2161,21 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
/* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel) | 0x200000); + MCHBAR32(0x4020 + 0x400 * channel) = + MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; }
/* refresh disable */ - write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); + MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8; FOR_ALL_POPULATED_CHANNELS { wait_428c(channel);
@@ -2245,15 +2183,14 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
/* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); }
@@ -2316,8 +2253,7 @@ FOR_ALL_POPULATED_RANKS { struct run rn = get_longest_zero_run(stat[slotrank], 255); - ctrl->timings[channel][slotrank].val_320c = - rn.middle - 127; + ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2341,7 +2277,7 @@
FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; }
FOR_ALL_POPULATED_CHANNELS { @@ -2405,10 +2341,9 @@ program_timings(ctrl, channel);
FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + - 4 * lane, 0); - read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + - 0x4140); + volatile u32 tmp; + MCHBAR32(0x4340 + 0x400 * channel + 4 * lane = 0; + tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); }
wait_428c(channel); @@ -2416,45 +2351,41 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x40411f4; + MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
/* DRAM command MRS * MR3 disable MPR */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
wait_428c(channel);
FOR_ALL_LANES { statistics[lane][edge] = - read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + - lane * 4); + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } } FOR_ALL_LANES { @@ -2479,21 +2410,20 @@ int channel, slotrank, lane; int err;
- write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0;
toggle_io_reset();
FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 4 * lane + - 0x400 * channel + 0x4080, 0); + MCHBAR32(4 * lane + 0x400 * channel + 0x4080) = 0; }
FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0, 0); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x400 * channel + - lane * 4 + 0x4140); + volatile u32 tmp; + tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); }
FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2513,43 +2443,37 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
/* DRAM command MRS * MR3 disable MPR */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
wait_428c(channel); } @@ -2573,72 +2497,65 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0;
/* DRAM command MRS * MR3 disable MPR */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); }
/* XXX: check any measured value ? */
FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + - lane * 4, - ~read32(DEFAULT_MCHBAR + 0x4040 + - 0x400 * channel + lane * 4) & 0xff); + MCHBAR32(0x4080 + 0x400 * channel + lane * 4) = + MCHBAR32(0x4040 + 0x400 * channel + lane * 4) + & 0xff; }
fill_pattern0(ctrl, channel, 0, 0xffffffff); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; }
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ - write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + MCHBAR32(0x4eb0) = 0x300; printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_real(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + falling_edges[channel][slotrank]); if (err) return err; }
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + MCHBAR32(0x4eb0) = 0x200; printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2648,7 +2565,7 @@ return err; }
- write32(DEFAULT_MCHBAR + 0x4eb0, 0); + MCHBAR32(0x4eb0) = 0;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = @@ -2662,8 +2579,7 @@ }
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2679,6 +2595,7 @@ int lower[NUM_LANES]; int upper[NUM_LANES]; int pat; + volatile u32 tmp;
FOR_ALL_LANES { lower[lane] = 0; @@ -2686,13 +2603,12 @@ }
for (i = 0; i < 3; i++) { - write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel, - reg3000b24[i] << 24); + MCHBAR32(0x3000 + 0x100 * channel) = reg3000b24[i] << 24; printram("[%x] = 0x%08x\n", 0x3000 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { @@ -2704,60 +2620,51 @@ program_timings(ctrl, channel);
FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4340 + - 0x400 * channel + 4 * lane, 0); - read32(DEFAULT_MCHBAR + 0x400 * channel + - 4 * lane + 0x4140); + MCHBAR32(0x4340 + 0x400 * channel + + 4 * lane) = 0; + tmp = MCHBAR32(0x400 * channel + + 4 * lane + 0x4140); } wait_428c(channel);
/* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0x4 | (ctrl->tRCD << 16) - | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << - 10)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, - 0x240); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = + 0x4 | (ctrl->tRCD << 16) | + (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) + << 10); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240;
/* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f201); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << - 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, - 0x242); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4234 + 0x400 * channel) = 0x8005020 | + ((ctrl->tWTR + ctrl->CWL + 8) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = + slotrank << 24; + MCHBAR32(0x4214 + 0x400 * channel) = 0x242;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x4005020 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, - 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x4005020 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + slotrank << 24; + MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
/* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x4340 + + tmp = MCHBAR32(0x4340 + 0x400 * channel + lane * 4); }
@@ -2789,7 +2696,7 @@ } }
- write32(DEFAULT_MCHBAR + 0x3000, 0); + MCHBAR32(0x3000) = 0; printram("CPA\n"); return 0; } @@ -2802,7 +2709,7 @@ int err;
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ - write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + MCHBAR32(0x4eb0) = 0x300; printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2812,7 +2719,7 @@ return err; }
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + MCHBAR32(0x4eb0) = 0x200; printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2822,7 +2729,7 @@ return err; }
- write32(DEFAULT_MCHBAR + 0x4eb0, 0); + MCHBAR32(0x4eb0) = 0;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = @@ -2835,8 +2742,7 @@ program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2845,49 +2751,35 @@ { wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) - << 10) | (ctrl->tRCD << 16) | 4); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + << 10) | (ctrl->tRCD << 16) | 4; + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
/* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x80011e0 | - ((ctrl->tWTR + ctrl->CWL + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + - 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + - 0x400 * channel, 0x242); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4234 + 0x400 * channel) = + 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4214 + 0x400 * channel) = 0x242;
/* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + - 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + - 0x400 * channel, - 0x40011e0 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + - 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + - 0x400 * channel, 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x40011e0 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
/* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + - 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + - 0x400 * channel, - 0x1001 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x420c + - 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + - 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0;
- write32(DEFAULT_MCHBAR + 0x4284 + - 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); }
@@ -2905,15 +2797,15 @@ upper[channel][slotrank][lane] = MAX_TIMC; }
- write32(DEFAULT_MCHBAR + 0x4ea8, 1); + MCHBAR32(0x4ea8) = 1; printram("discover timC write:\n");
for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { - write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100), - (rege3c_b24[i] << 24) - | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100)) - & ~0x3f000000)); + MCHBAR32(0xe3c + (channel * 0x100)) = + (rege3c_b24[i] << 24) | + (MCHBAR32(0xe3c + (channel * 0x100)) + & ~0x3f000000) udelay(2); for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { @@ -2925,7 +2817,8 @@ statistics[MAX_TIMC] = 1;
fill_pattern5(ctrl, channel, pat); - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = + 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; @@ -2968,13 +2861,12 @@ }
FOR_ALL_CHANNELS { - write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c, - 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) & - ~0x3f000000)); + MCHBAR32((channel * 0x100) + 0xe3c) = + 0 | (MCHBAR32((channel * 0x100) + 0xe3c) & ~0x3f000000); udelay(2); }
- write32(DEFAULT_MCHBAR + 0x4ea8, 0); + MCHBAR32(0x4ea8) = 0;
printram("CPB\n");
@@ -3024,11 +2916,10 @@ int channel, slotrank;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - write32(DEFAULT_MCHBAR + 0x0004 + (channel << 8) + - lane_registers[slotrank], make_mr0(ctrl, slotrank)); - write32(DEFAULT_MCHBAR + 0x0008 + (channel << 8) + - lane_registers[slotrank], - make_mr1(ctrl, slotrank, channel)); + MCHBAR32(0x0004 + (channel << 8) + lane_registers[slotrank]) = + make_mr0(ctrl, slotrank); + MCHBAR32(0x0008 + (channel << 8) + lane_registers[slotrank]) = + make_mr1(ctrl, slotrank, channel); } }
@@ -3038,7 +2929,7 @@
slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { + if (MCHBAR32(0x42a0 + (channel << 10)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; @@ -3046,45 +2937,45 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
- write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; }
for (slotrank = 0; slotrank < 4; slotrank++) FOR_ALL_CHANNELS if (ctrl->rankmap[channel] & (1 << slotrank)) { FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + (0x4f40 + 4 * lane), 0); - write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0); + MCHBAR32(0x4f40 + 4 * lane) = 0; + MCHBAR32(0x4d40 + 4 * lane) = 0; } wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006); - write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004); - write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10), - 0x00060000 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244); + MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006; + MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004; + MCHBAR32(0x4200 + (channel << 10)) = + 0x00060000 | (slotrank << 24); + MCHBAR32(0x4210 + (channel << 10)) = 0x00000244; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201); - write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064); - write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10), - 0x00000000 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242); + MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201; + MCHBAR32(0x4234 + (channel << 10)) = 0x08281064; + MCHBAR32(0x4204 + (channel << 10)) = + 0x00000000 | (slotrank << 24); + MCHBAR32(0x4214 + (channel << 10)) = 0x00000242; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105); - write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064); - write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10), - 0x00000000 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242); + MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105; + MCHBAR32(0x4238 + (channel << 10)) = 0x04281064; + MCHBAR32(0x4208 + (channel << 10)) = + 0x00000000 | (slotrank << 24); + MCHBAR32(0x4218 + (channel << 10)) = 0x00000242; /* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002); - write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01); - write32(DEFAULT_MCHBAR + 0x420c + (channel << 10), - 0x00060400 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x421c + (channel << 10), 0x00000240); - write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); + MCHBAR32(0x422c + (channel << 10)) = 0x0001f002; + MCHBAR32(0x423c + (channel << 10)) = 0x00280c01; + MCHBAR32(0x420c + (channel << 10)) = + 0x00060400 | (slotrank << 24); + MCHBAR32(0x421c + (channel << 10)) = 0x00000240; + MCHBAR32(0x4284 + (channel << 10)) = 0x000c0001; wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { + if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -3167,11 +3058,11 @@
dram_odt_stretch(ctrl, channel);
- write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10), + MCHBAR32(0x4008 + (channel << 10)) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) - | b4_8_12); + | b4_8_12; } }
@@ -3179,8 +3070,8 @@ { int channel; FOR_ALL_POPULATED_CHANNELS { - write32(DEFAULT_MCHBAR + (0x42a0 + 0x400 * channel), - 0x00001000 | ctrl->rankmap[channel]); + MCHBAR32(0x42a0 + 0x400 * channel) = + 0x00001000 | ctrl->rankmap[channel]; MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK } } @@ -3198,10 +3089,10 @@ int t3_ns; u32 r32;
- write32(DEFAULT_MCHBAR + 0x4cd4, 0x00000046); + MCHBAR32(0x4cd4) = 0x00000046;
- write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK - write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK + MCHBAR32(0x400c) = (MCHBAR32(0x400c) & 0xFFFFCFFF) | 0x1000; // OK + MCHBAR32(0x440c) = (MCHBAR32(0x440c) & 0xFFFFCFFF) | 0x1000; // OK
if (ctrl->mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3210,40 +3101,35 @@ /* APD - PPD, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_Config) = 0x00000340;
- write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK - write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK - write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK - write32(DEFAULT_MCHBAR + 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK + MCHBAR32(0x4380) = 0x00000aaa; // OK + MCHBAR32(0x4780) = 0x00000aaa; // OK + MCHBAR32(0x4f88) = 0x5f7003ff; // OK + MCHBAR32(0x5064) = 0x00073000 | ctrl->reg_5064b0; // OK
FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { /* Unpopulated channel. */ case 0: - write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0); + MCHBAR32(0x4384 + channel * 0x400) = 0; break; /* Only single-ranked dimms. */ case 1: case 4: case 5: - write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x373131); + MCHBAR32(0x4384 + channel * 0x400) = 0x373131; break; /* Dual-ranked dimms present. */ default: - write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x9b6ea1); + MCHBAR32(0x4384 + channel * 0x400) = 0x9b6ea1; break; } }
- write32 (DEFAULT_MCHBAR + 0x5880, 0xca9171e5); - write32 (DEFAULT_MCHBAR + 0x5888, - (read32 (DEFAULT_MCHBAR + 0x5888) & ~0xffffff) | 0xe4d5d0); - write32 (DEFAULT_MCHBAR + 0x58a8, read32 (DEFAULT_MCHBAR + 0x58a8) & ~0x1f); - write32 (DEFAULT_MCHBAR + 0x4294, - (read32 (DEFAULT_MCHBAR + 0x4294) & ~0x30000) - | (1 << 16)); - write32 (DEFAULT_MCHBAR + 0x4694, - (read32 (DEFAULT_MCHBAR + 0x4694) & ~0x30000) - | (1 << 16)); + MCHBAR32(0x5880) = 0xca9171e5; + MCHBAR32(0x5888) = MCHBAR32(0x5888) & ~0xffffff) | 0xe4d5d0; + MCHBAR32(0x58a8) = MCHBAR32(0x58a8) & ~0x1f; + MCHBAR32(0x4294) = MCHBAR32(0x4294) & ~0x30000 | (1 << 16); + MCHBAR32(0x4694) = MCHBAR32(0x4694) & ~0x30000 | (1 << 16);
MCHBAR32(0x5030) |= 1; // OK MCHBAR32(0x5030) |= 0x80; // OK @@ -3253,20 +3139,20 @@ FOR_ALL_POPULATED_CHANNELS break;
- t1_cycles = ((read32(DEFAULT_MCHBAR + 0x4290 + channel * 0x400) >> 8) & 0xff); - r32 = read32(DEFAULT_MCHBAR + 0x5064); + t1_cycles = (MCHBAR32(0x4290 + channel * 0x400) >> 8) & 0xff; + r32 = MCHBAR32(0x5064); if (r32 & 0x20000) t1_cycles += (r32 & 0xfff); - t1_cycles += (read32(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4) & 0xfff); + t1_cycles += MCHBAR32(channel * 0x400 + 0x42a4) & 0xfff; t1_ns = t1_cycles * ctrl->tCK / 256 + 544; if (!(r32 & 0x20000)) t1_ns += 500;
- t2_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f10) >> 8) & 0xfff); - if ( read32(DEFAULT_MCHBAR + 0x5f00) & 8 ) + t2_ns = 10 * ((MCHBAR32(0x5f10) >> 8) & 0xfff); + if (MCHBAR32(0x5f00) & 8) { - t3_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f20) >> 8) & 0xfff); - t3_ns += 10 * (read32(DEFAULT_MCHBAR + 0x5f18) & 0xff); + t3_ns = 10 * ((MCHBAR32(0x5f20) >> 8) & 0xfff); + t3_ns += 10 * (MCHBAR32(0x5f18) & 0xff); } else { @@ -3274,12 +3160,10 @@ } printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - write32 (DEFAULT_MCHBAR + 0x5d10, - ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) - | (encode_5d10(t1_ns) << 8) - | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) - | (read32(DEFAULT_MCHBAR + 0x5d10) & 0xC0C0C0C0) - | 0xc); + MCHBAR32(0x5d10) = ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | + (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | + (MCHBAR32(0x5d10) & 0xC0C0C0C0) | 0xc; }
void restore_timings(ramctr_timing * ctrl) @@ -3303,26 +3187,23 @@ }
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel - + 4 * lane, 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; }
FOR_ALL_POPULATED_CHANNELS - write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4008 + - 0x400 * channel) | 0x8000000); + MCHBAR32(0x4008 + 0x400 * channel) = + MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000;
FOR_ALL_POPULATED_CHANNELS { udelay (1); - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel) | 0x200000); + MCHBAR32(0x4020 + 0x400 * channel) = + MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; }
printram("CPE\n");
- write32(DEFAULT_MCHBAR + 0x3400, 0); - write32(DEFAULT_MCHBAR + 0x4eb0, 0); + MCHBAR32(0x3400) = 0; + MCHBAR32(0x4eb0) = 0;
printram("CP5b\n");
@@ -3366,14 +3247,13 @@
printram("CP5c\n");
- write32(DEFAULT_MCHBAR + 0x3000, 0); + MCHBAR32(0x3000) = 0;
FOR_ALL_CHANNELS { - write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c, - 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) & - ~0x3f000000)); + MCHBAR32(channel * 0x100 + 0xe3c) = + 0 | (MCHBAR32(channel * 0x100 + 0xe3c) & ~0x3f000000); udelay(2); }
- write32(DEFAULT_MCHBAR + 0x4ea8, 0); + MCHBAR32(0x4ea8) = 0; }