Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31322
Change subject: cpu/x86/mtrr: Fix _FROM_4G_TOP() macro ......................................................................
cpu/x86/mtrr: Fix _FROM_4G_TOP() macro
This macro was unnecessarily complex. Trying to avoid an overflow for unknown reasons, and instead shifted the result into the sign bit in C. Using a plain number seems to be safe in all languages.
This assumes that any processing entity (preprocessor, assembler, romcc, GCC) would complain if it can't handle the 4G number literal.
Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31322/1
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index eb7d78d..a15e186 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -150,7 +150,7 @@ #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x))
/* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ -#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) +#define _FROM_4G_TOP(x) (0x100000000 - (x))
/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression.