[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: update fsp_param setting based on latest baseline

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40349 )

Change subject: soc/intel/tigerlake: update fsp_param setting based on latest baseline
......................................................................

soc/intel/tigerlake: update fsp_param setting based on latest baseline

Merge the recent change from other platform(ICL/JSL).

Signed-off-by: Wonkyu Kim 
Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd
---
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 33 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/40349/1

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
old mode 100644
new mode 100755
index ff6d3a9..13c9139
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
 #include <fsp/util.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/xdci.h>
@@ -85,14 +86,21 @@
    /* Load VBT before devicetree-specific config. */
    params->GraphicsConfigPtr = (uintptr_t)vbt_get();

-	params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
-
+	/* Check if IGD is present and fill Graphics init param accordingly */
    dev = pcidev_path_on_root(SA_DEVFN_IGD);
    if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
    	params->PeiGraphicsPeimInit = 1;
    else
    	params->PeiGraphicsPeimInit = 0;

+	/* Use coreboot MP PPI services if Kconfig is enabled */
+	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+		params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+		params->SkipMpInit = 0;
+	} else {
+		params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+	}
+
    params->TcssAuxOri = config->TcssAuxOri;
    for (i = 0; i < 8; i++)
    	params->IomTypeCPortPadCfg[i] = 0x09000000;
@@ -127,7 +135,7 @@
    		get_l1_substate_control(config->PcieRpL1Substates[i]);

/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
    if (dev) {
    	if (!xdci_can_enable())
    		dev->enabled = 0;
@@ -142,7 +150,7 @@
    params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;

/* SATA */
-	dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
+	dev = pcidev_path_on_root(PCH_DEVFN_SATA);
    if (!dev)
    	params->SataEnable = 0;
    else {
@@ -156,7 +164,7 @@
    }

/* LAN */
-	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
+	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
    if (!dev)
    	params->PchLanEnable = 0;
    else
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
old mode 100644
new mode 100755
index 9933200..ac44ceb
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -20,8 +20,17 @@
    uint32_t mask = 0;
    const struct device *dev;

+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	if (!dev || !dev->enabled) {
+		/* Skip IGD initialization in FSP if device is disabled in devicetree.cb */
+		m_cfg->InternalGfx = 0;
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	} else {
+		m_cfg->InternalGfx = 1;
    /* Set IGD stolen size to 60MB. */
    m_cfg->IgdDvmt50PreAlloc = 0xFE;
+	}
+
    m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
    m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
    m_cfg->SaGv = config->SaGv;
@@ -60,22 +69,19 @@
    /* Disable BIOS Guard */
    m_cfg->BiosGuard = 0;

-	/* UART Debug Log */
+	/* Set debug interface flags */
    m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
-			DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB :
-			DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB;
-	m_cfg->PcdIsaSerialUartBase = 0x0;
-	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+		DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;

-	/*
-	 * Skip IGD initialization in FSP if device
-	 * is disable in devicetree.cb.
-	 */
-	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	if (!dev || !dev->enabled)
-		m_cfg->InternalGfx = 0;
-	else
-		m_cfg->InternalGfx = 0x1;
+	/* TraceHub configuration */
+	dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
+	if (dev && dev->enabled && config->TraceHubMode) {
+		m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
+		m_cfg->PchTraceHubMode = config->TraceHubMode;
+		m_cfg->CpuTraceHubMode = config->TraceHubMode;
+	}
+
+	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;

/* ISH */
    dev = pcidev_path_on_root(PCH_DEVFN_ISH);