[coreboot-gerrit] [S] Change in coreboot[main]: src/security/intel/txt/romstage.c: make romstage init work on SOC_INT...

[Filip Lewiński (Code Review)]

Attention is currently required from: Michał Kopeć, Michał Żygowski.

Hello Michał Żygowski, Michał Kopeć,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/82694?usp=email

to review the following change.

Change subject: src/security/intel/txt/romstage.c: make romstage init work on SOC_INTEL platforms
......................................................................

src/security/intel/txt/romstage.c: make romstage init work on SOC_INTEL platforms

Change-Id: I892c9eff16d51adc94b75c9ef9f0f1be4f50bada
Signed-off-by: Michał Żygowski 
Signed-off-by: Michał Kopeć 
---
M src/security/intel/txt/romstage.c
1 file changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/82694/1

diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c
index 643e7a9..c128198 100644
--- a/src/security/intel/txt/romstage.c
+++ b/src/security/intel/txt/romstage.c
@@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <acpi/acpi.h>
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/cr.h>
 #include <device/mmio.h>
+#include <cpu/x86/msr.h>
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_PMC)
+#include <intelblocks/pmclib.h>
+#endif
+#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMBASE)
 #include <southbridge/intel/common/pmbase.h>
+#endif
+#include <timer.h>
 #include <types.h>

#include "txt.h"
@@ -82,8 +90,12 @@
    	}

/* FIXME: Clear SLP_TYP# */
-		write_pmbase32(4, read_pmbase32(4) & ~(0x7 << 10));
-
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_PMC)
+		pmc_disable_pm1_control(SLP_TYP);
+#endif
+#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMBASE)
+		write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SLP_TYP);
+#endif
    	intel_txt_run_sclean();

/* If running the BIOS ACM is impossible, manual intervention is required */