[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Fix PMC config

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37784 )

Change subject: soc/intel/tigerlake: Fix PMC config
......................................................................

soc/intel/tigerlake: Fix PMC config

Fix PMC base address for tigerlake.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi 
Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784
Tested-by: build bot (Jenkins) 
Reviewed-by: Wonkyu Kim 
Reviewed-by: Nick Vaccaro 
Reviewed-by: Shaunak Saha 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/tigerlake/bootblock/pch.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Shaunak Saha: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Nick Vaccaro: Looks good to me, approved
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 7a93182..1654809 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -40,7 +40,7 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>

-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x0600
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x1100
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0x0980
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4