Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32117 )
Change subject: soc/intel/cannonlake: Configure Vmx support using Kconfig ......................................................................
soc/intel/cannonlake: Configure Vmx support using Kconfig
Change VmxEnable UPD values based on Kconfig ENABLE_VMX and remove it from Devicetree and chip.h
Remove Vmx dependency on Vt-d
Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32117 Reviewed-by: Lijian Zhao lijian.zhao@intel.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 4 files changed, 2 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Patrick Rudolph: Looks good to me, approved Lijian Zhao: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1507214..9ecbf00 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -22,7 +22,6 @@ register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e4a92a9..625655b 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -26,7 +26,6 @@ register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 7461d78..58b540c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -354,7 +354,6 @@
/* Intel VT configuration */ uint8_t VtdDisable; - uint8_t VmxEnable;
/* * Acoustic Noise Mitigation diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 4545f52..2ad2c93 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -61,11 +61,8 @@ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
- /* Disable Vmx if Vt-d is already disabled */ - if (config->VtdDisable) - m_cfg->VmxEnable = 0; - else - m_cfg->VmxEnable = config->VmxEnable; + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))