[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Lance Zhao, Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph.
Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Thejaswani Putta, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/61352

to look at the new patch set (#6).

Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
......................................................................

soc/intel/common/block/pcie/rtd3: Add PM methods to the device.

Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.

Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.

Signed-off-by: Cliff Huang 
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
---
M src/soc/intel/common/block/pcie/rtd3/chip.h
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
2 files changed, 104 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/6