Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50467 )
Change subject: i2c/tpm: increase timeout for waiting cr50 ......................................................................
i2c/tpm: increase timeout for waiting cr50
Timeout for waiting cr50 to report correct did:vid pair was 150ms. However we've seen that this might take up to 256ms on Zork platform, probably since verstage starts earlier within the PSP.
Increase timeout to 300ms so verstage doesn't trigger recovery mode by TPM init failure. In most cases increasing timeout won't be a problem since we exit eary if we get the response from the cr50.
BUG=b:179829104, b:178656936, b:176909783 BRANCH=zork TEST=build and boot on dirinboz
Signed-off-by: Kangheui Won khwon@chromium.org Change-Id: Ib9534f18148d323099fe43777e91ab74c3ff2cfd --- M src/drivers/i2c/tpm/cr50.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/50467/1
diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8e12d1f..d627e85 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -445,13 +445,13 @@ int retries;
/* - * 150 ms should be enough to synchronize with the TPM even under the + * 300 ms should be enough to synchronize with the TPM even under the * worst nested reset request conditions. In vast majority of cases * there would be no wait at all. */ printk(BIOS_INFO, "Probing TPM I2C: ");
- for (retries = 15; retries > 0; retries--) { + for (retries = 30; retries > 0; retries--) { int rc;
rc = cr50_i2c_read(chip, TPM_DID_VID(0), (uint8_t *)did_vid, 4);