Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47106 )
Change subject: sb/intel/bd82x6x/sata.c: Simplify RMW operations ......................................................................
sb/intel/bd82x6x/sata.c: Simplify RMW operations
Introduce the `sir_unset_and_set_mask` helper and simplify a PCI register update to not use an intermediate variable.
Change-Id: Ibb33aef755bba1ae48e6029fcab0687d9faf62b4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 13 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47106/1
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 2b46cfa..a83dd63 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -28,6 +28,14 @@ pci_write_config32(dev, SATA_SIRD, value); }
+static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_read_resources(struct device *dev) { struct resource *res; @@ -90,7 +98,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; u8 sata_mode; @@ -120,10 +127,8 @@ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + /* Port enable + OOB retry mode */ + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map | 0x8000);
/* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); @@ -204,19 +209,10 @@ /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); sir_write(dev, 0x28, 0xa0000033); - reg32 = sir_read(dev, 0x54); - reg32 &= 0xff000000; - reg32 |= 0x5555aa; - sir_write(dev, 0x54, reg32); + sir_unset_and_set_mask(dev, 0x54, 0xffffff, 0x5555aa); sir_write(dev, 0x64, 0xcccc8484); - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0xcccc; - sir_write(dev, 0x68, reg32); - reg32 = sir_read(dev, 0x78); - reg32 &= 0x0000ffff; - reg32 |= 0x88880000; - sir_write(dev, 0x78, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0xcccc); + sir_unset_and_set_mask(dev, 0x78, 0xffff0000, 0x88880000); sir_write(dev, 0x84, 0x001c7000); sir_write(dev, 0x88, 0x88338822); sir_write(dev, 0xa0, 0x001c7000);