[coreboot-gerrit] [XS] Change in coreboot[main]: soc/qualcomm/sc7280: Increase romstage/verstage section for clang

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80639?usp=email )

Change subject: soc/qualcomm/sc7280: Increase romstage/verstage section for clang
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soc/qualcomm/sc7280: Increase romstage/verstage section for clang

Clang builds slightly larger binaries so increase the section.

Change-Id: Ide01233f209613678c5408f1afab19415c1071be
Signed-off-by: Arthur Heymans 
---
M src/soc/qualcomm/sc7280/memlayout.ld
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/80639/1

diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld
index 231b9fe..be9cb70 100644
--- a/src/soc/qualcomm/sc7280/memlayout.ld
+++ b/src/soc/qualcomm/sc7280/memlayout.ld
@@ -25,9 +25,9 @@
    AOPSRAM_END(0x0B100000)

SSRAM_START(0x14680000)
-	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 104K)
-	REGION(qcsdi, 0x1469A000, 44K, 4K)
-	REGION(modem_id, 0x146A5D00, 4, 4)
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 112K)
+	REGION(qcsdi, 0x1469C000, 44K, 4K)
+	REGION(modem_id, 0x146A7000, 4, 4)
    SSRAM_END(0x146AB000)

BSRAM_START(0x14800000)