Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44802 )
Change subject: soc/intel/elkhartlake: Do initial SoC commit till ramstage ......................................................................
Patch Set 7: Code-Review+2
(4 comments)
https://review.coreboot.org/c/coreboot/+/44802/5/src/soc/intel/elkhartlake/K... File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/44802/5/src/soc/intel/elkhartlake/K... PS5, Line 184: config CBFS_SIZE : hex : default 0x200000
Good idea. […]
So far we do have a mixed situation of where this value is defined. While for instance Ice Lake, Jasper Lake Skylake and Tiger Lake have this switch defined on chipset level, Apollo Lake, Braswell and Kaby Lake does not. In any way, mainboard is always able to override thie size. So this is nothing urgent.
https://review.coreboot.org/c/coreboot/+/44802/5/src/soc/intel/elkhartlake/K... PS5, Line 189: default "src/vendorcode/intel/fsp/fsp2_0/elkhartlake/"
Usually FSP upd will be published post PV. […]
OK, fine with me.
https://review.coreboot.org/c/coreboot/+/44802/3/src/soc/intel/elkhartlake/c... File src/soc/intel/elkhartlake/chip.h:
https://review.coreboot.org/c/coreboot/+/44802/3/src/soc/intel/elkhartlake/c... PS3, Line 63: uint32_t tcc_offset;
this is the UPD entry for FSP S TCC (Thermal Control Circuit) Activation Offset
Ok, understand.
https://review.coreboot.org/c/coreboot/+/44802/5/src/soc/intel/elkhartlake/s... File src/soc/intel/elkhartlake/smmrelocate.c:
https://review.coreboot.org/c/coreboot/+/44802/5/src/soc/intel/elkhartlake/s... PS5, Line 172: char
Will revisit this later.
Sure.