Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31951
Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device ......................................................................
device/pciexp_device: Add set_L1_ss_latency() for pciexp device
This patch performs below operations
1. Add new function to perform L1 latency programming for PCIE devices.
2. Remove duplicate implementaion of PCIE L1 latency programming and refer the same from common pciexp_device.c.
Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/device/pciexp_device.c M src/include/device/pciexp.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c 4 files changed, 17 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31951/1
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 318f8cd..e4af9b2 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -463,6 +463,14 @@ pciexp_enable_ltr(dev); }
+void pciexp_set_L1_ss_max_latency(struct device *dev, unsigned int offset) +{ + /* Set max snoop and non-snoop latency for the SOC */ + pci_write_config32(dev, offset, + PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | + PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); +} + void pciexp_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 121b998..459eef5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -5,6 +5,11 @@ /* PCI-E Sub-System ID */ #define PCIE_SUBSYSTEM_VENDOR_ID 0x94
+/* Latency tolerance reporting, max non-snoop latency value 3.14ms */ +#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 +/* Latency tolerance reporting, max snoop latency value 3.14ms */ +#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 + enum aspm_type { PCIE_ASPM_NONE = 0, PCIE_ASPM_L0S = 1, @@ -29,4 +34,6 @@ void pciexp_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device);
+void pciexp_set_L1_ss_max_latency(struct device *dev, unsigned int offset); + #endif /* DEVICE_PCIEXP_H */ diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index fdb8782..72e9884 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,15 +649,9 @@ root_port_commit_config(); }
-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) -{ - /* Set max snoop and non-snoop latency for Broadwell */ - pci_write_config32(dev, off, 0x10031003); -} - static struct pci_operations pcie_ops = { .set_subsystem = pciexp_set_subsystem, - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_L1_ss_latency = pciexp_set_L1_ss_max_latency, };
static struct device_operations device_ops = { diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 1c3114b..f02c38b 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -21,10 +21,6 @@ #include <device/pci_ops.h>
#define CACHE_LINE_SIZE 0x10 -/* Latency tolerance reporting, max non-snoop latency value 3.14ms */ -#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 -/* Latency tolerance reporting, max snoop latency value 3.14ms */ -#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
static void pch_pcie_init(struct device *dev) { @@ -62,16 +58,8 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); }
-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) -{ - /* Set max snoop and non-snoop latency for the SOC */ - pci_write_config32(dev, offset, - PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | - PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); -} - static struct pci_operations pcie_ops = { - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_L1_ss_latency = pciexp_set_L1_ss_max_latency, .set_subsystem = pciexp_set_subsystem, };