James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39021 )
Change subject: nb/intel/snb: Add PCI routing table for PEG root ports ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG@9 PS1, Line 9: Previously the PRTs were defined in southbridge code (#13612), but this
Thanks, noted.
Done
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG@18 PS1, Line 18: > snd_hda_intel 0000:01:00.1: PCI INT B: no GSI
Thanks, noted.
Done
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG@20 PS1, Line 20: Tested with GIGABYTE P67A-UD3R (#31363) with Radeon HD 5670.
nomsi gives the same results as with MSI. […]
The command line should be pci=nomsi, MSIs can also be disabled in the snd_hda_intel driver with enable_msi=0. Verified with /proc/interrupts that MSIs aren't used and done.
https://review.coreboot.org/c/coreboot/+/39021/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/39021/1/src/northbridge/intel/sandy... PS1, Line 47: }
If I'm not mistaken, we can just re-use the IRQM method of the PCH code. e.g. […]
Yes, thanks. :)
https://review.coreboot.org/c/coreboot/+/39021/1/src/northbridge/intel/sandy... PS1, Line 137: Package() { 0x0000ffff, 0, 0, 16 },
Let's just take 19, 16, 17, 18 / D, A, B, C then. If all sources say the same, […]
Done.