[coreboot-gerrit] Change in coreboot[master]: [WIP] [Don't Merge]: PO Safe Config

[Meera Ravindranath (Code Review)]

Hello Subrata Banik,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48527

to review the following change.

Change subject: [WIP] [Don't Merge]: PO Safe Config
......................................................................

[WIP] [Don't Merge]: PO Safe Config

Change-Id: I7cce423de924e7056e88b52a2443c554fd9123ac
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48527/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index a21ca4a..f176785 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -273,7 +273,7 @@
    	sizeof(config->PcieRpClkReqDetect));

params->PmSupport = 1;
-	params->Hwp = 1;
+	params->Hwp = 0;
    params->Cx = 1;
    params->PsOnEnable = 1;