[coreboot-gerrit] Patch merged into coreboot/master: Smaug: Add NVDEC and TSEC carveouts

the following patch was just integrated into master:
commit 0bdb88b106ec65e3d1296d61545e09ecdab0794f
Author: Tom Warren 
Date:   Mon Aug 3 14:58:11 2015 -0700

Smaug: Add NVDEC and TSEC carveouts

The NV security team requested that coreboot allocate the NVDEC
    and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB)
    and TSEC (2 regions, splitting 2MB), and set their lock bits.
    Kernel/trusted code should be able to use the regions now.

Note that this change sets the UNLOCKED bit in Carveout1Cfg0
    and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files
    (both 3GB and 4GB BCTs) so that the BOMs can be written.
    Any future revisions to these BCT files should take this
    into account.

BUG=None
    BRANCH=None
    TEST=Built and booted on my P5 A44. Saw the carveout regions
    in the boot spew, and CBMEM living just below the last region
    (TSEC). Dumped the MC GeneralizedCarveoutX registers and
    verified their values (same as BCT, with only BOM/CFG0 changed).

Signed-off-by: Patrick Georgi 
    Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23
    Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0
    Original-Signed-off-by: Tom Warren 
    Original-Reviewed-on: https://chromium-review.googlesource.com/290452
    Original-Reviewed-by: Furquan Shaikh 
    Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60)
    Original-Reviewed-on: https://chromium-review.googlesource.com/291081
    Original-Commit-Queue: Furquan Shaikh 
    Original-Trybot-Ready: Furquan Shaikh 
    Original-Tested-by: Furquan Shaikh

Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5
    Reviewed-on: http://review.coreboot.org/11381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer

See http://review.coreboot.org/11381 for details.

-gerrit