Patrick Havelange has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33573
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33573/1
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 43e0647..ae61e6d 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -182,7 +182,7 @@ #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
// GPIO Input Route SCI -#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10) +#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) #define N_PCH_GPIO_RX_SCI_ROUTE 19 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01