Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40643 )
Change subject: soc/baytrail/raminit: Populate SMBIOS type 17 tables ......................................................................
soc/baytrail/raminit: Populate SMBIOS type 17 tables
Populate SMBIOS type 17 tables using data from SPD and read via IOSF. Refactor print_dram_info() to pass thru SPD data and channel/speed info. Move call to print_dram_info() after cbmem initialization so the SMBIOS data has somewhere to go.
Test: build/boot google/swanky, verify via dmidecode.
Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/soc/intel/baytrail/romstage/raminit.c 1 file changed, 27 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40643/1
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index f1a3c17..1f6309f 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -8,6 +8,7 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> @@ -20,6 +21,7 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h> +#include <spd_bin.h>
uintptr_t smbus_base(void) { @@ -55,7 +57,27 @@ do_putchar(b); }
-static void print_dram_info(void) +static void populate_smbios_tables(void *dram_data, int speed, int num_channels) +{ + spd_raw_data spd; + dimm_attr dimm; + enum spd_status status; + + /* copy raw data into spd struct */ + memcpy(&spd, dram_data, SPD_PAGE_LEN); + + /* decode into dimm_attr struct */ + status = spd_decode_ddr3(&dimm, spd); + + /* some SPDs have bad CRCs, nothing we can do about it */ + if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) { + /* add table 17 entry for each channel */ + for (int i = 0; i < num_channels; i++) + spd_add_smbios17(i, 0, speed, &dimm); + } +} + +static void print_dram_info(void *dram_data) { const int mrc_ver_reg = 0xf0; const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); @@ -95,6 +117,8 @@ speed = 1600; break; } printk(BIOS_INFO, "%dMHz\n", speed); + + populate_smbios_tables(dram_data, speed, num_channels); }
void raminit(struct mrc_params *mp, int prev_sleep_state) @@ -147,8 +171,6 @@
ret = mrc_entry(mp);
- print_dram_info(); - if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { @@ -159,6 +181,8 @@ #endif }
+ print_dram_info(mp->mainboard.dram_data[0]); + printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, mp->data_to_save_size);