Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8168
-gerrit
commit 3f34e3db0352ac600e7c149748d665f579842538 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Thu Jan 8 02:05:21 2015 +1100
soc/intel/broadwell/spi_loading.c: Remove dead code
I would appear from commit a6354a1 that this is now dead code.
Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/spi_loading.c | 67 ----------------------------------- 2 files changed, 68 deletions(-)
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 43be95e..feead00 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -52,7 +52,6 @@ smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += spi_loading.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c deleted file mode 100644 index 9454d03..0000000 --- a/src/soc/intel/broadwell/spi_loading.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -}