Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58756 )
Change subject: asus/am1i-a: update the PIRQ routing table ......................................................................
asus/am1i-a: update the PIRQ routing table
Update the PIRQ routing in accordance with the new IRQ tables.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: Ib9933246c9af523b3e7820b92102572295e77ce1 --- M src/mainboard/asus/am1i-a/irq_tables.c 1 file changed, 29 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58756/1
diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c index 3e0606e..94b5ef6 100644 --- a/src/mainboard/asus/am1i-a/irq_tables.c +++ b/src/mainboard/asus/am1i-a/irq_tables.c @@ -9,27 +9,42 @@ 0x00, /* Interrupt router bus */ (0x14 << 3) | 0x3, /* Interrupt router dev */ 0, /* IRQs devoted exclusively to PCI usage */ - 0x1002, /* Vendor */ - 0x439d, /* Device */ + 0x1022, /* Vendor */ + 0x780e, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x3b, /* Checksum (has to be set to some value that + 0x5e, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). */ /* clang-format off */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x11 << 3) | 0x0, {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, - {0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, - {0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + /* bus, dev | fn, {{link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap} }, slot, rfu */ + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* PCIe GPP to dGPU 1:00.00: 0:02.01 - IRQ 3 */ + /* PCIe GPP to Eth 2:00.00: 0:02.05 - IRQ 4 */ + {0x00, (0x02 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0} }, 0x0, 0x0}, + /* USB XHCI: 0:10.00 - IRQ 5 */ + {0x00, (0x10 << 3) | 0x0, {{0x03, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* SATA: 0:11.00 - IRQ 7 */ + {0x00, (0x11 << 3) | 0x0, {{0x04, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + /* USB EHCI1: 0:12.02 - IRQ 4 */ + {0x00, (0x12 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + /* USB EHCI2: 0:13.02 - IRQ 4 */ + {0x00, (0x13 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + /* USB EHCI3: 0:16.02 - IRQ 4 */ + {0x00, (0x16 << 3) | 0x0, {{0x03, 0xccb0}, {0x02, 0xccb0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0} }, 0x0, 0x0}, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.01 PCIe GPP - IRQ 3 */ + {0x01, (0x00 << 3) | 0x0, {{0x01, 0xccb0}, {0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0} }, 0x1, 0x0}, + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:02.05 PCIe GPP - IRQ 4 */ + {0x02, (0x00 << 3) | 0x0, {{0x02, 0xccb0}, {0x03, 0xccb0}, {0x04, 0xccb0}, {0x01, 0xccb0} }, 0x2, 0x0} } /* clang-format on */ };