[coreboot-gerrit] Change in coreboot[master]: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48270 )

Change subject: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller
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Patch Set 2:
> Patch Set 2:
>
> I'm not seeing it yet.  Can you let me know (offline's OK) what doc you're looking at?

see the chapter FCH/registers/GPIO pin control registers/GPIO registers of #55570. There are 4 banks of GPIOs (0-3) and they start 0x100 bytes apart from each other, so 0x400 bytes in total