Hello Patrick Rudolph, EricR Lai, Bernardo Perez Priego, Aamir Bohra, Selma Bensaid, Tim Wawrzynczak, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36519
to look at the new patch set (#12).
Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating ......................................................................
soc/intel/cannonlake: Disable USB2 PHY Power gating
Workaround to disable USB2 PHY power gating to fix issue seen when Apple 87W USB-C charger is connected in S0ix state on WHL platforms (based on Intel's recommendation - https://cdrdv2.intel.com/v1/dl/getContent/599886). Issue is seen on CML platforms also. So,disable power gating for Drallion.
Add devicetree entry to set the flag to disable/enable USB2 PHY power gating for different CNL PCH based platforms
BUG=b:133775942 TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if the system wakes up after that
Signed-off-by: Surendranath Gurivireddy surendranath.r.gurivireddy@intel.com Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 6 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36519/12