Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43919 )
Change subject: mb/asrock/h110m: Relocate devicetree FSP settings ......................................................................
mb/asrock/h110m: Relocate devicetree FSP settings
Some settings are suspicious, and have been annotated with FIXMEs.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 77 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/43919/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 977fa29..b299b41 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -28,17 +28,10 @@ register "dptf_enable" = "1"
# FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "SkipExtGfxScan" = "0" register "PrimaryDisplay" = "Display_PEG" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "PchHdaVcType" = "Vc1"
@@ -125,8 +118,6 @@ .voltage_limit = 1520 \ }"
- register "EnableLan" = "0" - # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" @@ -142,6 +133,7 @@ register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" @@ -153,25 +145,6 @@ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
- # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - # SATA4 and SATA5 are located in the lower right corner of the board, - # but they are not populated. This is because the same PCB is used to - # make boards with better PCHs, which can have up to six SATA ports. - # However, the H110 PCH only has four SATA ports, which explains why - # two connectors are missing. - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - # PCH UART, SPI, I2C register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ @@ -187,55 +160,6 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }"
- # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Disable CLKREQ#, since onboard LAN is always present - register "PcieRpClkReqSupport[5]" = "0" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - # PL2 override 91W register "power_limits_config" = "{ .tdp_pl2_override = 91, @@ -253,11 +177,19 @@ end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + register "Peg0MaxLinkWidth" = "Peg0_x16" + + # Configure PCIe clockgen in PCH + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end - device pci 04.0 on end # Thermal Subsystem + device pci 04.0 on # Thermal Subsystem + register "Device4Enable" = "1" + end device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 @@ -270,8 +202,11 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -279,6 +214,23 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA subsystemid 0x1849 0xa102 + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + # SATA4 and SATA5 are located in the lower right corner of the board, + # but they are not populated. This is because the same PCB is used to + # make boards with better PCHs, which can have up to six SATA ports. + # However, the H110 PCH only has four SATA ports, which explains why + # two connectors are missing. + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" end device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 @@ -287,9 +239,33 @@ device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 on # PCI Express Port 5 - PCIE slot + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" + register "PcieRpHotPlug[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 - Onboard LAN + register "PcieRpEnable[5]" = "1" + + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device pci 1c.6 on # PCI Express Port 7 - PCIE slot + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "3" + register "PcieRpHotPlug[6]" = "1" + end device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -299,10 +275,15 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC + device pci 1e.4 off # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end + device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43
chip superio/common @@ -412,9 +393,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end