[coreboot-gerrit] Change in ...coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 )

Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
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Patch Set 6:

(1 comment)
> Patch Set 6:
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> (1 comment)

https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster.... 
File src/soc/intel/braswell/southcluster.c:

https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster.... 
PS6, Line 621:
> > Matt, can you test if serirq is enabled by the Google blob? […]

Checking the bits on addresses (ilb_base + ILB_OIC) and (ilb_base + SCNT)?

If Chromebooks have any hardware component utilizing SERIRQ, there should be interrupts reported in /proc/interrupts for that device. Example, SuperIO serial port:
- with disabled SERIRQ no interrupts reported from serial port
- SERIRQ in continuous mode, interrupts from serial appear on all cores through IOAPIC irq4