Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: /mb/google/hatch: Create nightfury variant ......................................................................
/mb/google/hatch: Create nightfury variant
Create new variant for nightfury
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage and boot on nightfury proto board
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: raymondchung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 506 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 783ec73..26e96a2 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -98,6 +98,7 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e216135..1ec4e87 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -43,6 +43,11 @@ select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384
+config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc new file mode 100644 index 0000000..c57d090 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -0,0 +1,28 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 +SPD_SOURCES += 16G_2666_2bg # 0b1000 +SPD_SOURCES += 16G_3200_4bg # 0b1001 + +bootblock-y += gpio.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c new file mode 100644 index 0000000..2bf97b1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* C12 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : EMMC_DATA0 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : EMMC_DATA1 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : EMMC_DATA2 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : EMMC_DATA3 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : EMMC_DATA4 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : EMMC_DATA5 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : EMMC_DATA6 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : EMMC_DATA7 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..ffa7590 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 70 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 70 +#define DPTF_CPU_ACTIVE_AC1 65 +#define DPTF_CPU_ACTIVE_AC2 60 +#define DPTF_CPU_ACTIVE_AC3 50 +#define DPTF_CPU_ACTIVE_AC4 40 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 62 +#define DPTF_TSR0_CRITICAL 105 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 54 +#define DPTF_TSR1_CRITICAL 105 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 12000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h new file mode 100644 index 0000000..92f9d41 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb new file mode 100644 index 0000000..f3f6c3b --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -0,0 +1,177 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_off_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end + +end diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +}