Attention is currently required from: Nico Huber, Matt DeVillier, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 )
Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS1:
All datasheets I looked at say LPC BIOS_CNTL is 8 bits, and
eSPI and SPI BIOS_CNTL is 32 bits. I've never seen 16 bits so far. It might not matter, though, if the LPC register doesn't mind bigger reads/writes.
I agree that the eSPI and SPI BIOS_CNTL register is 32 bits wide. I'll fix this right now.
Intel......... eSPI and LPC/SPI are both 32 bits, too. Intel just didn't mention that in the datasheet. Source: refcode and Intel doc#545845.
"LPC/SPI"? LPC and eSPI share the same PCI device/function number (D31F0), but SPI is D31F5.
AFAICS the fast_spi code does get used by eSPI as well bc the spi part of eSPI is compatible and since the BIOS_CONTROL register and the status bit have the same offset, it will get cleared on eSPI, too.
Please read the datasheets again. LPC and eSPI are on D31F0, whereas SPI is on D31F5. And the fast_spi code uses `PCH_DEV_SPI`, which is D31F5.
There are google boards with kbl, cnl and others, that could be tested. @Tim @Matt
As I said in the commit message, eSPI is out of the scope of this patch. I'll happily review any changes to fix eSPI-related stuff, but I cannot test this myself. I recorded my observations in the commit message because the documentation about SPI is garbage, and I would expect that eSPI documentation is of similar pedigree.