[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Use native CAR teardown

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48467 )

Change subject: soc/intel/xeon_sp: Use native CAR teardown
......................................................................

soc/intel/xeon_sp: Use native CAR teardown

This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's.

Note that ramstage CPU init sets up different final MTRRs anyway.

TESTED on ocp/deltalake and ocp/tiogapass.

Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/memmap.c
2 files changed, 16 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 6c10c35..d84a80e 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -67,6 +67,8 @@
    select HAVE_SMI_HANDLER
    select X86_SMM_LOADER_VERSION2
    select REG_SCRIPT
+	select NO_FSP_TEMP_RAM_EXIT
+	select INTEL_CAR_NEM # For postcar only now

config MAINBOARD_USES_FSP2_0
      bool
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index cd81754..0af0ad2 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -29,17 +29,22 @@

void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	/*
-	 * We need to make sure ramstage will be run cached. At this
-	 * point exact location of ramstage in cbmem is not known.
-	 * Instruct postcar to cache 16 megs under cbmem top which is
-	 * a safe bet to cover ramstage.
-	 */
-	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	uintptr_t cbmem_base;
+	size_t cbmem_size;

+	/* Try account for the CBMEM region currently used and for future use */
+	cbmem_get_region((void **)&cbmem_base, &cbmem_size);
    printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
-	top_of_ram -= 16 * MiB;
-	postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK);
+	printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size);
+	/* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */
+	cbmem_base -= 4 * MiB;
+	cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB);
+
+	/* Align the top to make sure we don't use too many MTRR's */
+	cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB);
+
+	postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK);
    /* Cache the TSEG region */
    if (CONFIG(TSEG_STAGE_CACHE))
    	postcar_enable_tseg_cache(pcf);