HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48933 )
Change subject: src/*/*/*/bootblock.c: Cosmetic clean-up and fix includes ......................................................................
src/*/*/*/bootblock.c: Cosmetic clean-up and fix includes
Change-Id: I7bf14167b35365fe918a854a32f84262f9793d25 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/emulation/qemu-q35/bootblock.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/soc/intel/broadwell/bootblock.c 4 files changed, 52 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/48933/1
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index efb3a4f..ce1ab16 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -12,24 +12,21 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + uint32_t reg32;
/* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit + * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final assumption is that + * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + reg32 = 0; + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, reg32); + reg32 = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
/* MCFG is now active. If it's not qemu was started for machine PC */ if (CONFIG(BOOTBLOCK_CONSOLE) && @@ -43,8 +40,7 @@ enable_spi_prefetching_and_caching();
/* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
void bootblock_soc_init(void) diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index a0e8fc0..1672db7 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,28 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h> -#include <device/pci_ops.h> +#include <arch/pci_ops.h>
#include "gm45.h"
void bootblock_early_northbridge_init(void) { - uint32_t reg; + uint32_t reg32;
/* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit + * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final assumption is that + * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + reg32 = 0; + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, reg32); + reg32 = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index dad61f9..5026fce 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,25 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h> -#include <device/pci_ops.h> +#include <arch/pci_ops.h> + #include "sandybridge.h"
void bootblock_early_northbridge_init(void) { - uint32_t reg; + uint32_t reg32;
/* - * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all - * subsequent non-explicit config accesses use MCFG. This code also assumes - * that bootblock_northbridge_init() is the first thing called in the non-asm - * boot block code. The final assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all subsequent + * non-explicit config accesses use MCFG. This code also assumes that + * bootblock_northbridge_init() is the first thing called in the non-asm boot block code. + * The final assumption is that no assembly code is using the CONFIG(MMCONF_SUPPORT) + * option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - reg = 0; - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + reg32 = 0; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg32); + reg32 = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index 5edfaee..cb36757 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -1,28 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> +#include <arch/pci_ops.h> + +#include "soc/pci_devs.h" +#include "soc/systemagent.h"
void bootblock_early_northbridge_init(void) { - uint32_t reg; + uint32_t reg32;
/* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit + * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final assumption is that + * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + reg32 = 0; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg32); + reg32 = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg32); }