Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81784?usp=email )
Change subject: southbridge/intel/common/acpi: Update sleepstates.asl ......................................................................
southbridge/intel/common/acpi: Update sleepstates.asl
sleepstates.asl will be widely used by Xeon-SP as well. For Xeon-SP, only S0 and S5 are supported.
Change-Id: I8ee0d8600f72c6d732e685a46dc89c7e24de8334 Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/southbridge/intel/common/acpi/sleepstates.asl 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/81784/1
diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl index 14ed86e..51475d8 100644 --- a/src/southbridge/intel/common/acpi/sleepstates.asl +++ b/src/southbridge/intel/common/acpi/sleepstates.asl @@ -1,11 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */
/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ +#if CONFIG(XEON_SP_COMMON_BASE) +Name (SSFG, 0x00) +#else #if CONFIG(HAVE_ACPI_RESUME) Name (SSFG, 0x0D) #else Name (SSFG, 0x09) #endif +#endif
If (CONFIG(ACPI_S1_NOT_SUPPORTED)) { SSFG &= 0xfe