Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30998 )
Change subject: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout ......................................................................
Patch Set 1:
(1 comment)
This change is ready for review.
https://review.coreboot.org/#/c/30998/1/src/soc/amd/stoneyridge/include/soc/... File src/soc/amd/stoneyridge/include/soc/gpio.h:
https://review.coreboot.org/#/c/30998/1/src/soc/amd/stoneyridge/include/soc/... PS1, Line 465: #define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS)
We do it both ways in plenty of places in the coreboot code. […]
"just 0" would (silently) imply GPIO_TIMEBASE_61uS, which is just one of 4 possible "zeros".
To make the "have coreboot preset the exact same values as kernel" work, we are relying on it choosing exactly the GPIO_TIMEBASE_61uS 0.
Thus, IMHO it is better to be explicit.