[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38512 )

Change subject: soc/intel/skylake: Make TPM reserve area from 20KB to 32KB
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38512/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38512/2//COMMIT_MSG@12 
PS2, Line 12: For CR50 TPM device the MMIO size requirement is 32KB (0x8000).
Is this the same Cr50 I'm familiar with? i.e. h1? It's not connected on a bus that can memory map anything nor can the hardware support it without an assist from a host controller somewhere else. I'm perplexed by the motivation of this patch.