Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48444 )
Change subject: soc/intel/elkhartlake: Update PCI device definition ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48444/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48444/1//COMMIT_MSG@7 PS1, Line 7: pci dev
PCI device
Done
https://review.coreboot.org/c/coreboot/+/48444/1//COMMIT_MSG@9 PS1, Line 9: pci dev
PCI device
Done
https://review.coreboot.org/c/coreboot/+/48444/1/src/soc/intel/elkhartlake/i... File src/soc/intel/elkhartlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/48444/1/src/soc/intel/elkhartlake/i... PS1, Line 35:
extra TAB, please remove
Done
https://review.coreboot.org/c/coreboot/+/48444/1/src/soc/intel/elkhartlake/i... PS1, Line 85: define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) : #define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5)
At least according to the EDS this should be CSE_2 and CSE_3. […]
I just checked BIOS source codes and other projects, seems like the numbering in EDS should starts from 1 instead of 0. Let me ask for EDS update internally, thanks for pointing out!