[coreboot-gerrit] [M] Change in coreboot[main]: drivers/intel/dtbt: Add discrete Thunderbolt driver

[Tim Crawford (Code Review)]

Attention is currently required from: Jeremy Soller, Kyösti Mälkki, Martin L Roth, Michał Żygowski, Paul Menzel, Tim Wawrzynczak, Utkarsh H Patel.

Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75286?usp=email )

Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver
......................................................................

Patch Set 9:

(3 comments)

File src/drivers/intel/dtbt/dtbt.c:

https://review.coreboot.org/c/coreboot/+/75286/comment/3476c984_0ed3e940?usp... :
PS6, Line 13: #define PCIE2TBT 0x54C
> Referring to older datasheet: Alpine-Ridge DP, Thunderbolt Interface Controller, Revision 1. […]

Titan Ridge and Maple Ridge BIOS implementation guides document only these 2 specific offsets.

DP Thunderbolt Interface Controller is mentioned only as a reference document in the Titan Ridge guide.

https://review.coreboot.org/c/coreboot/+/75286/comment/8fc10b00_2cc947d7?usp... :
PS6, Line 24: #define TIMEOUT_MS 1000
> Is there a reason why you don't use this timeout with acpigen_write_delay_until_namestr_int() calls? […]

The BIOS implementation guides specify a default timeout of 600ms for `GO2SX`/`GO2SX_NO_WAKE` acknowledgement.

https://review.coreboot.org/c/coreboot/+/75286/comment/885e2f62_e3de1345?usp... :
PS6, Line 37: 	if (!wait_ms(TIMEOUT_MS, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) {
> My old reference for PCIE2TBT_GO2SX command says clearing VALID would not clear DONE. […]

Maple Ridge BIOS implementation guide does not specify the timeout after clearing `PCIE2TBT`.

Titan Ridge BIOS implementation guide does show it in the flowchart "Figure 2.3: Mailbox Command Handshake Procedure". The only thing that then references this handshake is `OS_UP` though.