[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38252 )

Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T
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soc/intel/common/block/cpu/car: Enable caching before FSP-T

This patch is required for Boot Guard enabled platform. Enable caching
before entering FSP-T.

TEST=Stitch boot guard ACM with signed KM and BPM &&
     Enable FSP-T and boot all the way to the OS &&
     Read MSR 0x13a and esnure boot guard verified boot and
     measured boot are enabled.

Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24
---
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38252/1

diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 091fc4a..fd22903 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -35,6 +35,12 @@
 cache_as_ram:
    post_code(0x21)

+	/* Enable caching */
+	mov %cr0, %eax
+	and $~(CR0_CD | CR0_NW), %eax
+	invd
+	mov %eax, %cr0
+
    /* find fsp in cbfs */
    lea	fsp_name, %esi
    mov	$1f, %esp