Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31253
Change subject: RFC: riscv: Add initial support for 32bit boards ......................................................................
RFC: riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * Should we choose between rv32/rv64 per stage? ARCH_BOOTBLOCK_RISCV_RV32? How can we do that without having a separate rv32 toolchain?
TEST=Boots to "Payload not loaded." on 32bit qemu
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug philipp@hug.cx --- M src/arch/riscv/Makefile.inc M src/arch/riscv/bootblock.S M src/arch/riscv/include/arch/smp/atomic.h M src/arch/riscv/include/bits.h M src/arch/riscv/include/mcall.h M src/arch/riscv/ramstage.S M src/arch/riscv/smp.c M src/lib/libgcc.c M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig.name M src/mainboard/emulation/spike-riscv/Kconfig M src/soc/ucb/riscv/Kconfig 12 files changed, 89 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31253/1
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 9d91f0c..d5f6295 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -86,6 +86,10 @@ bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags)
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_bootblock += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_BOOTBLOCK_RISCV
################################################################################ @@ -116,6 +120,10 @@ romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags)
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_romstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_ROMSTAGE_RISCV
################################################################################ @@ -161,5 +169,9 @@ ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags)
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_ramstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_RAMSTAGE_RISCV endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index d4b8be7..b0796f9 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -16,6 +16,7 @@ */
#include <arch/encoding.h> +#include <bits.h> #include <mcall.h>
.section ".text._start", "ax", %progbits @@ -44,7 +45,7 @@ slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1
diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h index de7fd19..8030844 100644 --- a/src/arch/riscv/include/arch/smp/atomic.h +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -47,7 +47,7 @@ # define atomic_inc(v) atomic_add(v, 1) # define atomic_dec(v) atomic_add(v, -1) #else -static inline int atomic_add(atomic_t *v, int inc) +static inline int atomic_add(volatile atomic_t *v, int inc) { long flags = disable_irqsave(); int res = v->counter; @@ -56,7 +56,7 @@ return res; }
-static inline int atomic_swap(atomic_t *v, int swp) +static inline int atomic_swap(volatile atomic_t *v, int swp) { long flags = disable_irqsave(); int res = v->counter; diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h index f69c7ec..d824f3e 100644 --- a/src/arch/riscv/include/bits.h +++ b/src/arch/riscv/include/bits.h @@ -47,10 +47,19 @@ #define STR(x) XSTR(x) #define XSTR(x) #x
-# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LOG_REGBYTES 3 +#if __riscv_xlen == 64 +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu +#define LOG_REGBYTES 3 +#else +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw +#define LOG_REGBYTES 2 +#endif
#define REGBYTES (1 << LOG_REGBYTES)
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index cd1ed6d..192d2b4 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -18,7 +18,13 @@
// NOTE: this is the size of hls_t below. A static_assert would be // nice to have. +#if __riscv_xlen == 64 #define HLS_SIZE 88 +#endif + +#if __riscv_xlen == 32 +#define HLS_SIZE 52 +#endif
/* We save 37 registers, currently. */ #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) @@ -26,6 +32,7 @@ #ifndef __ASSEMBLER__
#include <arch/encoding.h> +#include <arch/smp/atomic.h> #include <stdint.h>
typedef struct { @@ -38,8 +45,8 @@ struct blocker { void *arg; void (*fn)(void *arg); - uint32_t sync_a; - uint32_t sync_b; + atomic_t sync_a; + atomic_t sync_b; };
typedef struct { diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 115a55f..28183e5 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -14,6 +14,7 @@ */
#include <arch/encoding.h> +#include <bits.h> #include <mcall.h>
.section ".text._start", "ax", %progbits @@ -27,7 +28,7 @@ slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 8942ec5..b32e4b8 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -32,13 +32,13 @@ /* waiting for work hart */ do { barrier(); - } while (SYNCA != 0x01234567); + } while (atomic_read(&SYNCA) != 0x01234567);
clear_csr(mstatus, MSTATUS_MIE); write_csr(mie, MIP_MSIP);
/* count how many cores enter the halt */ - __sync_fetch_and_add(&SYNCB, 1); + atomic_add(&SYNCB, 1);
do { barrier(); @@ -49,17 +49,17 @@ } else { /* Initialize the counter and * mark the work hart into smp_pause */ - SYNCB = 0; - SYNCA = 0x01234567; + atomic_set(&SYNCB, 0); + atomic_set(&SYNCA, 0x01234567);
/* waiting for other Hart to enter the halt */ do { barrier(); - } while (SYNCB + 1 < CONFIG_MAX_CPUS); + } while (atomic_read(&SYNCB) + 1 < CONFIG_MAX_CPUS);
/* initialize for the next call */ - SYNCA = 0; - SYNCB = 0; + atomic_set(&SYNCA, 0); + atomic_set(&SYNCB, 0); } #undef SYNCA #undef SYNCB diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 99a0749..3e5bef8 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -20,7 +20,7 @@ * <lib.h> in case GCC does not have an assembly version for this arch. */
-#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ +#if !IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_ARCH_RISCV_RV32) /* work around lack of --gc-sections on x86 */ int __clzsi2(u32 a); int __clzsi2(u32 a) { diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index ecaa764..d15c99e 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -16,6 +16,21 @@ # util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf # qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf
+ +if BOARD_EMULATION_QEMU_RISCV_RV64 + +config BOARD_EMULATION_QEMU_RISCV + def_bool y + select ARCH_RISCV_RV64 +endif + +if BOARD_EMULATION_QEMU_RISCV_RV32 + +config BOARD_EMULATION_QEMU_RISCV + def_bool y + select ARCH_RISCV_RV32 +endif + if BOARD_EMULATION_QEMU_RISCV
config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig.name b/src/mainboard/emulation/qemu-riscv/Kconfig.name index e9243e6..61fd919 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig.name +++ b/src/mainboard/emulation/qemu-riscv/Kconfig.name @@ -1,2 +1,5 @@ -config BOARD_EMULATION_QEMU_RISCV - bool "QEMU riscv" +config BOARD_EMULATION_QEMU_RISCV_RV64 + bool "QEMU RISC-V rv64" + +config BOARD_EMULATION_QEMU_RISCV_RV32 + bool "QEMU RISC-V rv32" diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index f8c98ab..03046f72 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -16,6 +16,7 @@
config BOARD_SPECIFIC_OPTIONS def_bool y + select ARCH_RISCV_RV64 select SOC_UCB_RISCV select BOARD_ROMSIZE_KB_4096 select DRIVERS_UART_8250MEM diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index aa352d9..ad48c1c 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,5 +1,4 @@ config SOC_UCB_RISCV - select ARCH_RISCV_RV64 select ARCH_RISCV_S select ARCH_RISCV_U select ARCH_RISCV_PMP @@ -15,6 +14,8 @@
if SOC_UCB_RISCV
+if ARCH_RISCV_RV64 + config RISCV_ARCH string default "rv64imafd" @@ -27,6 +28,24 @@ string default "medany"
+endif + +if ARCH_RISCV_RV32 + +config RISCV_ARCH + string + default "rv32im" + +config RISCV_ABI + string + default "ilp32" + +config RISCV_CODEMODEL + string + default "medany" + +endif + config RISCV_WORKING_HARTID int default 0