[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemag...

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41471 )

Change subject: soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41471/6/src/soc/intel/broadwell/acp... 
File src/soc/intel/broadwell/acpi/systemagent.asl:

https://review.coreboot.org/c/coreboot/+/41471/6/src/soc/intel/broadwell/acp... 
PS6, Line 156: 	If (Local0 == Local1) {
I don't think any chipset code reserves this region. I don't know why we
can't repurpose the ME space in this case. In most cases it is covered by
remapped DRAM maybe that is allowed but PCI resources are not? In any case,
we need to align C and ASL code.