Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4587
-gerrit
commit 54b40eedb527a4d591088290ea5a5ab7ca1ddcb5 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sun Dec 29 19:33:06 2013 -0500
RFC: console: Make 8250 memmaped console independent of Oxford PCIe952
RFC: Request for comments. DO NOT MERGE (YET)
Running the console on an 8250-compatible memory-mapped UART was only possible via an Oxford PCIe952 adapter, as the console code explicitly depended on variables and functions defined by the Oxford driver.
Change-Id: Icde4cdb2d671865502293183aed5664e8690a9ac Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/arch/x86/lib/romstage_console.c | 5 +-- src/console/console.c | 6 +-- src/drivers/oxford/oxpcie/Makefile.inc | 1 + src/drivers/oxford/oxpcie/oxpcie_early.c | 13 ++++-- src/drivers/oxford/oxpcie/oxpcie_memconsole.c | 62 +++++++++++++++++++++++++++ src/include/uart8250.h | 9 ++-- src/lib/uart8250mem.c | 53 +---------------------- 7 files changed, 81 insertions(+), 68 deletions(-)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 68b10eb..0ab0187 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -40,10 +40,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r');
#if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/console/console.c b/src/console/console.c index 38ac3e7..c0d3f2c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -106,11 +106,11 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE
-#if CONFIG_CONSOLE_SERIAL +#if CONFIG_CONSOLE_SERIAL && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif -#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM - oxford_init(); +#if CONFIG_CONSOLE_SERIAL8250MEM + uart_mem_init(); #endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 6cc29c4..b967e02 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -2,4 +2,5 @@ ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_memconsole.c endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4..ed6a7ff 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -38,7 +38,12 @@ #if defined(__PRE_RAM__) int oxford_oxpcie_present CAR_GLOBAL;
-void oxford_init(void) +u32 uart8250_mem_get_baseaddr(void) +{ + return CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +} + +u32 uart_mem_init(void) { u16 reg16; oxford_oxpcie_present = 1; @@ -92,7 +97,7 @@ void oxford_init(void) */ id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; + return -1; device = OXPCIE_DEVICE_3; break; case 0xc1581415: /* e.g. Startech MPEX2S952 */ @@ -101,7 +106,7 @@ void oxford_init(void) default: /* No UART here. */ oxford_oxpcie_present = 0; - return; + return -1; }
/* Setup base address on device */ @@ -117,6 +122,8 @@ void oxford_init(void) u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + + return uart0_base; }
#endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_memconsole.c b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c new file mode 100644 index 0000000..d1d0ce4 --- /dev/null +++ b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Subject to the GNU GPL version 2. + */ + +#include <uart8250.h> +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#include "option_table.h" +#endif + +u32 uart_mem_init(void) +{ + unsigned uart_baud = CONFIG_TTYS0_BAUD; + u32 uart_bar = 0; + unsigned div; + + /* find out the correct baud rate */ +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) && CONFIG_USE_OPTION_TABLE + b_index = read_option(baud_rate, 0); + b_index &= 7; + uart_baud = baud[b_index]; +#else + if (get_option(&b_index, "baud_rate") == CB_SUCCESS) + uart_baud = baud[b_index]; +#endif +#endif + + /* Now find the UART base address and calculate the divisor */ + +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) + device_t dev = dev_find_device(0x1415, 0xc158, NULL); + if (!dev) + dev = dev_find_device(0x1415, 0xc11b, NULL); + + if (dev) { + struct resource *res = find_resource(dev, 0x10); + + if (res) { + uart_bar = res->base + 0x1000; // for 1st UART + // uart_bar = res->base + 0x2000; // for 2nd UART + } + } + + if (!uart_bar) +#endif + uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART + // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART + + div = 4000000 / uart_baud; + + if (uart_bar) + uart8250_mem_init(uart_bar, div); + + return uart_bar; +} diff --git a/src/include/uart8250.h b/src/include/uart8250.h index a3868c5..493e32a 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,6 +20,8 @@ #ifndef UART8250_H #define UART8250_H
+#include <types.h> + /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -130,13 +132,8 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); +u32 uart8250_mem_get_baseaddr(void);
-#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; - -void oxford_init(void); -#endif #endif
#endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..39dec37 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,8 +20,8 @@
#include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> #if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> #include "option_table.h" #endif #include <device/device.h> @@ -102,54 +102,3 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* Set to 3 for 8N1 */ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } - -u32 uart_mem_init(void) -{ - unsigned uart_baud = CONFIG_TTYS0_BAUD; - u32 uart_bar = 0; - unsigned div; - - /* find out the correct baud rate */ -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - uart_baud = baud[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - uart_baud = baud[b_index]; -#endif -#endif - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE - -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - - if (dev) { - struct resource *res = find_resource(dev, 0x10); - - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } - - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART - - div = 4000000 / uart_baud; -#endif - - if (uart_bar) - uart8250_mem_init(uart_bar, div); - - return uart_bar; -}