[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE

[Elyes Haouas (Code Review)]

Attention is currently required from: Christian Walter, Dinesh Gehlot, Felix Singer, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tim Crawford.

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email )

Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
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Patch Set 3:

(1 comment)

Patchset:

PS3: 
One question please:
We have USE_DDR4 and USE_DDR5, so why you don't use those kconfig symbols and then use SPD size already defined at "include/device/dram/ddr{4,5}.h" ?