Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74517?usp=email )
(
4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/cometlake: Enable early caching of RAMTOP region ......................................................................
soc/intel/cometlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.
Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable).
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: I579f85e84e0aba7f192ff81a6725d65b7f79ff75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74517 Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 33025eb..9e6ca2a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -29,7 +29,8 @@ select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC - select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP
config SOC_INTEL_COMETLAKE_1 bool