[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Make use of clflush in common platform_segment_loaded

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34992 )

Change subject: soc/intel/common: Make use of clflush in common platform_segment_loaded
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Patch Set 2:
> Patch Set 2:
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> (3 comments)
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> Move to cpu/x86? I don't think it is Intel specific.

this is to enable WB capability in caching between romstage end and postcar. you can follow the topic CLs