[coreboot-gerrit] Change in coreboot[master]: mb/google/zork/vilboz: make PCIE_RST1_L take effect

[Peichao Li (Code Review)]

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42089 )

Change subject: mb/google/zork/vilboz: make PCIE_RST1_L take effect
......................................................................

mb/google/zork/vilboz: make PCIE_RST1_L take effect

BUG=b:157499341
BRANCH=None
TEST=check waveform via oscilloscope when power on

Signed-off-by: peichao.wang 
Change-Id: I619ed2f98ebadc45a57d6ce3f81e75f42aa75a88
---
M src/mainboard/google/zork/variants/vilboz/Makefile.inc
A src/mainboard/google/zork/variants/vilboz/romstage.c
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42089/1

diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc
index dc1e411..ab4604c 100644
--- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc
+++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc
@@ -2,4 +2,6 @@

subdirs-y += ./spd

+romstage-y += romstage.c
+
 ramstage-y += variant.c
diff --git a/src/mainboard/google/zork/variants/vilboz/romstage.c b/src/mainboard/google/zork/variants/vilboz/romstage.c
new file mode 100644
index 0000000..b8a51a1
--- /dev/null
+++ b/src/mainboard/google/zork/variants/vilboz/romstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <stddef.h>
+#include <soc/romstage.h>
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+void variant_romstage_entry(void)
+{
+	/* SET PCIE_RST1_L HIGH */
+	gpio_set(PCIE_RST1_L, 1);
+}