[coreboot-gerrit] [M] Change in coreboot[master]: sb/intel/common: Rename and inline {read,write}_pmbaseX()

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Werner Zeh.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70049 )

Change subject: sb/intel/common: Rename and inline {read,write}_pmbaseX()
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Patch Set 4:

(1 comment)

File src/southbridge/intel/common/pmbase.h:

https://review.coreboot.org/c/coreboot/+/70049/comment/899e2bbe_65b5d401 
PS4, Line 14: #elif CONFIG(TCO_SPACE_NOT_YET_SPLIT)
            : /* Must let TCO registers 0x60..0x80 through. */
            : #define PMSIZE 0x80
            : #elif CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS)
            : /* TCO registers 0x60..0x80 moved, these are now GPEs. */
            : #define PMSIZE 0x80
> What about  […]

Well removal of TCO_SPACE_NOT_YET_SPLIT is already in the queue. Once split, TCO registers would no longer use pm_ but tco_ variants, like what soc/intel had already introduced to the tree.

We pickup DEFAULT_PMBASE or ACPI_BASE_ADDRESS from <soc/iomap.h> so I might just place the PMSIZE definitions there.