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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/991d28d7_06642365
PS47, Line 107: };
What I meant is that we have now the flags declaration for board config […]
Oh,do you mean move it up? Will do clean up here. We want to put the FSP common things together and keep it simple for further developer. This is why we are trying to do.
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