Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44223 )
Change subject: cpu/intel/socket_441/Makefile.inc: Order entries ......................................................................
cpu/intel/socket_441/Makefile.inc: Order entries
Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special.
Tested with BUILD_TIMELESS=1, Intel D945GCLF remains identical.
Change-Id: I6762a00e12a2290fb566df3149746731c5f675a5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/socket_441/Makefile.inc 1 file changed, 14 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44223/1
diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e21bf03..d827747 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,15 +1,17 @@ -subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - -bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c -postcar-y += ../car/p4-netburst/exit_car.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S
romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + +subdirs-y += ../model_106cx + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc