[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add bootram reservations

[Felix Held (Code Review)]

Felix Held has uploaded a new patch set (#5) to the change originally created by Marshall Dawson. ( https://review.coreboot.org/c/coreboot/+/38702 )

Change subject: soc/amd/picasso: Add bootram reservations
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soc/amd/picasso: Add bootram reservations

Picasso consumes DRAM to avoid running XIP from the boot flash.  This
must be reserved from use by the OS.  During bootblock, save the region
used by the stage (and reserve 0 for verstage).  Save romstage's
region in romstage.  Override the weak bootmem_platform_add_ranges() to
retrieve the bases and sizes, then add them as BM_MEM_RESERVED.

Note the design of verstage, as it applies to the x86, is T.B.D.  The
reservation of its bootram should be reevaluated later.

Change-Id: I7032117bbf12b845e06df8cfa7a62445e589ecf5
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/bootblock/bootblock.c
M src/soc/amd/picasso/northbridge.c
M src/soc/amd/picasso/romstage.c
3 files changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38702/5