Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik.
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86277?usp=email )
Change subject: soc/intel/pantherlake: Add ability to set SaGv work points ......................................................................
soc/intel/pantherlake: Add ability to set SaGv work points
Hook up SaGv work point upds.
BUG=none TEST=Boot to OS.
Signed-off-by: Bora Guvendik bora.guvendik@intel.com Change-Id: Ie38d007edc293727066f2bc9f67037e6fbe77aa5 --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/86277/1
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 5b96891..4c5b36d 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -62,6 +62,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { + unsigned int i; + m_cfg->SaGv = config->sagv; if (m_cfg->SaGv) { /* @@ -73,6 +75,11 @@ m_cfg->SaGvWpMask = config->sagv_wp_bitmap; else m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; + + for (i = 0; i < HOB_MAX_SAGV_POINTS; i++) { + m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; + m_cfg->SaGvGear[i] = config->sagv_gear[i]; + } }
if (config->max_dram_speed_mts)