Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34662 )
Change subject: Documentation/binaries: Add AMD FSP documentation ......................................................................
Patch Set 7:
(21 comments)
Patch Set 1:
Initial documentation on FSP.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... File Documentation/binaries/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 32: 1. **Memory fragmentation** : Though FSP still fragments memory, it has added control for flexibility : of where the chunks will reside.
Asked Alex to change it.
Just removed this section. Might be returned if Alex provides a good explanation.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 36: intergers
Asked Alex to change it.
Rewritten to better explain this.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 37: 3. **UPD with no UEFI dependencies** : UPD interface can be made C99 or C11 compatible with no hard dependencies : to UEFI.
From a spread sheet he filled up yesterday... you can see what he wrote.
Re-declared as TBD.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 40: 4. **Platform specific code**
Needs more discussion
Currently removed.
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... PS2, Line 40: 4. **Platform specific code** : Similar to AGESA, FSP will make call back to platform specific code. :
I don't know, ask Alex at conference call today. The document he provided me was vague...
Removed.
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 1: # FSP implementation differences between Intel and AMD
Partially done.
No comparison with Intel now.
https://review.coreboot.org/c/coreboot/+/34662/6/Documentation/binaries/amd/... PS6, Line 25: > obtain the memory map from the PSP.
For patch set 8.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 10: he Family 17h differences from older AMD and Intel CPU/SOC are:
I don't agree. […]
I have rephrased the whole introduction, I do hope you like it better.
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 13: PSP loads a section of code (a header in the : SPI tells which code and where to load) into RAM and gives control to : it.
Thanks, will consider it.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 17: Reset vector is not the old 0xFFFFFFF0.
I guess I misunderstood what you wanted. Will rephrase (and perhaps join with the one above).
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 20: This document
Will do.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 27: FSP-T calls are
Not at this time, and I can't think of any reason why we would use it. […]
Ack
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 32: FSP-M
I'm going to rewrite this, as Martin explained that FSP-M still does a lot of chip initialization.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 33: emory
Oops
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 37: The PSP typically loads the boot vector and associated code into RAM.
Will change some of it. […]
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 42: This is an engineering decision still : yet to be made.
From Alex: Looks like he wants to make it position independent, but is having problems to achieve it […]
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 47: 1. Memory fragmentation : : Though FSP still fragments memory, it has added control for flexibility : of where the chunks will reside.
Will do.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 54: don’t
Shall we discuss this with Alex? This is his statement.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 59: can be made
Will remove.
Done
https://review.coreboot.org/c/coreboot/+/34662/7/Documentation/binaries/amd/... PS7, Line 64: Similar to AGESA, FSP will call back to platform specific code.
Not sure on this one. I understood one way from what Alex wrote, than he contradicts me. […]
Done
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/cavi... File Documentation/binaries/cavium/index.md:
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/cavi... PS2, Line 7: ## Platform initialization : - [AMD FSP](AMD_FSP_family_17h.md)
Should have been removed when I copy/pasted... will remove.
Done