[coreboot-gerrit] Change in coreboot[master]: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47682 )

Change subject: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47682/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47682/2//COMMIT_MSG@9 
PS2, Line 9: set the latency to <64us
> Where is that limit documented, that means, where does it come from?

The PCI spec defines the possible values for the exit latency, 64us just happens to be what was recommended by genesys.